The present invention relates generally to semiconductor processes, and more particularly to device source/ drain contact structure.
A key challenge for high performance CMOS devices is the external parasitic resistance. Up till now, resistances from some resistive components, such as a contact with a tungsten (W) plug are not playing a critical role but will become a growing issue as plug resistance rapidly climbs in the coming generations. If not resolved, this resistance increase may approach or even exceed junction extension resistance in value. Introducing Cu at the contact level was presented as a possible solution to retard the parasitic effects on transistor drive current and circuit delay caused by increased resistance of the contact with the W plug upon scaling.
However, based on an earlier study by S. Demuynck, replacing the W-fill material by Cu does not result in a significant contact resistance reduction. The reason is that even though the Cu resistance is low, a significant portion of the overall contact resistance comes from a barrier metal, which is still made of the high resistance W.
Barrier-free direct-contact-via (DCV) structures, which has been widely used for copper interconnects between two metal layers. However such structures cannot be used for a so called “first contact layer” that makes connections between Metal 1 and transistors, because the Cu will diffuse through a silicide layer and will lead to significant yield loss.
As such, what is desired is a new contact structure that has a lower contact resistance.